The intent is to create an EDA ready spin of Rocky Linux, complete with these features out of the box :
"pyeda · PyPI" https://pypi.org/project/pyeda/
PandA-bambu – framework for research in high-level synthesis and HW/SW co-design
QElectroTech – Electronic diagrams
WaveDrom – draws your Timing Diagram or Waveform from simple textual description
Electric – IC design with schematic capture, layout, routing, LVS, PCB layout
Fritzing – Schematic capture and PCB layout
gEDA – Schematic capture
KiCad – PCB layout
KTechLab – Electronic and PIC microcontroller design
LibrePCB – PCB Layout
LTspice – SPICE simulation, schematic capture, waveform viewer, Analog Devices
PCB – PCB layout
pcb-rnd – PCB layout
Alliance/Coriolis – VHDL compiler, simulator, logic synthesizer, automatic place and route
Chisel – Hardware compiler framework
cocotb – coroutine based co-simulation testbench environment for verifying VHDL and SystemVerilog using Python
Edalize – Python library for interfacing EDA tools (Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus)
FuseSoc – package manager and a set of build tools for HDL code.
GHDL – G HDL, a VHDL analyzer, compiler, simulator and synthesizer
Gnucap – GNU Circuit Analysis Package
Icarus Verilog – Verilog simulator (free)
ipyxact – Python based IP-XACT parser
IRSIM – switch-level simulator
LiteX – Migen/MiSoC based Core/SoC builder
Magic – IC layout, extraction, DRC
Migen – Python toolbox for HDL design
Netgen – Layout Versus Schematic (LVS) tool
nMigen – Python based HDL design
Ngspice – SPICE circuit simulation
OpenRAM – Memory compiler development framework
OpenROAD – RTL to GDS in 24 hours, no human in the loop
OpenSTA – Static Timing Analyzer
Oregano – schematic capture and SPICE circuit simulation
Qrouter – multi-level, over-the-cell maze router
Qucs – Quite Universal Circuit Simulator
RePlAce – global placement tool
SpinalHDL – HDL that creates VHDL or Verilog
Verilator – Verilog simulator
XCircuit – Schematic capture for SPICE netlists and PostScript
Yosys – Verilog RTL synthesis
Project IceStorm – Lattice bitstream format documentation
Qflow – digital synthesis flow using Verilog or VHDL, targets Xilinx or Altera
nextpnr – FPGA place and route
SymbiFlow – FPGA framework for tools, Verilog to bitstream
https://tree.taiga.io/project/preachermanx-rocky-eda/timeline
2.2. Application streams
Red Hat Enterprise Linux 8 introduces the concept of Application Streams. Multiple versions of user space components are now delivered and updated more frequently than the core operating system packages. This provides greater flexibility to customize Red Hat Enterprise Linux without impacting the underlying stability of the platform or specific deployments.
Components made available as Application Streams can be packaged as modules or RPM packages, and are delivered through the AppStream repository in Red Hat Enterprise Linux 8. Each Application Stream has a given life cycle, either the same as RHEL 8 or shorter, more suitable to the particular application. Application Streams with a shorter life cycle are listed in the Red Hat Enterprise Linux 8 Application Streams Life Cycle page.
Modules are collections of packages representing a logical unit: an application, a language stack, a database, or a set of tools. These packages are built, tested, and released together.
Module streams represent versions of the Application Stream components. For example, two streams (versions) of the PostgreSQL database server are available in the postgresql module: PostgreSQL 10 (the default stream) and PostgreSQL 9.6. Only one module stream can be installed on the system. Different versions can be used in separate containers.
Detailed module commands are described in the Installing, managing, and removing user-space components document. For a list of modules available in AppStream, see the Package manifest.